RISC architecture

RISC, Reduced Instruction Set Computer is an architecture mainly for microcontrollers. It works as per the LOAD-STORE model, where we execute different instructions for loading and storing data.

Design philosophy

  • RISC aims to decrease main memory access as much as possible. So, most instructions are register based, and therefore fast.
  • All of the instructions are of the same size and perform operations on same sized data. Hence, these instructions are parallelizable.
  • Fetch, decode, execute cycle is standard and similar for all instructions.
  • Fewer addressing modes, therefore smaller instruction set, which is also easier to learn.
  • Has more number of registers compared to CISC.
  • More power efficient as most instructions are register based.
  • Hardwired control unit is used, which means smaller in size and lesser area. Many features like timers, ADC, DAC are provided in chip.
  • Follows Von Neumann architecture.