IO techniques

Programmed I/O

  • Triggered by I/O instructions in a program.
  • The CPU issues commands to the I/O module if the module isn't busy by setting a few bits in the control register.
  • The I/O module issues the command to an I/O device and watches over it.
  • When the task is done, the I/O module sets the necessary status bits in its control register, which the CPU is constantly watching over.
  • The CPU then moves the input data over to a CPU register.
    (This is slightly similar to how serial communication on an 8051 works)
    programmed_io.png

Addressing modes

Fully separate I/O

The data, address and control lines are fully individual to I/O and memory.

Isolated I/O

  • The data and address buses are common for I/O and memory.
  • But the read-write control lines are different
    isolated_io.excalidraw.svg
    Cons:
  • Slower operations
  • More complex programming

Memory mapped I/O

  • The data, address and control lines are all common for memory and I/O.
  • I/O literally occupies addresses that should have been part of main memory's address space. It is as if the I/O module is a memory chip itself.
    memory_mapped_io.excalidraw.svg
    Cons:
  • Limited address space
  • Slower response time
    isolate_mapped_io_diff.png
    Pros:
  • Simple to implement. Doesn't require special hardware/software.
    Cons:
  • Super inefficient as it stalls the CPU till it finishes.
  • CPU can only be as fast as the peripherals.

Interrupts driven I/O

  • Very similar to Programmed I/O but it is interrupt driven
  • CPU does its normal tasks and only focuses on the I/O module when it receives an interrupt.
  • Up until then the interface monitors the device and not the CPU.
  • On interrupt, CPU executes the ISR and resumes its tasks.

Direct Memory Access

In this method, the DMA controller takes complete control of the buses, writes directly to memory, bypassing the CPU.

  • The DMAC sends a BR (bus request) to the CPU asking to give up control of the bus.
  • The CPU responds with a BG (bus grant) after putting the address, data and read-write lines into high impedance.
  • After the transfer, the DMAC disables BR.
  • CPU resumes normal operation.

Different ways of DMA transfer

  1. Burst transfer: A sequence of words is transferred in a continuous burst.
  2. Cycle stealing: Only one word is transferred at a time after which bus control is given up to the CPU.

Configurations

  1. Single bus with detached DMA: Each transfer suspends CPU twice - I/O to DMA, DMA to memory.
  2. Single but with integrated DMA: Each transfer suspends CPU once - DMA to memory. The I/O module has a DMA integrated and doesn't transfer to DMA via bus unlike the previous config.
  3. Seperate I/O bus: CPU is suspended only once. There is a separate bus for I/O which interacts with the memory via the DMA and then the data bus.

Working

dma_controller.png
Has three registers to store address, number of words to be transferred and mode of transfer (the three blue registers). BG = 1: DMA writes to memory. BG = 0: CPU writes to DMA or reads from DMA. RD/WR are bi-directional and used depending on BG.

  1. CPU sends
    1. starting address of memory block (that is to be read or written) to the DMA
    2. Word count
    3. Control - read/write
    4. A control signal to start the transfer
  2. Peripheral makes a DMA request.
  3. DMAC makes a bus request.
  4. CPU grants a bus grant.
  5. DMAC places the address on the address bus and activates read or write.
  6. DMAC sends an acknowledgement to the peripheral.

Direct Cache Access

DCA is just DMA but instead of main memory, it loads data to cache directly.
This eliminates the extra step of CPU fetching from main memory into cache with plain DMA.

  • Based on hints from TLP, (the hints contain info about which blocks might be need in cache) the CPU prefetches the blocks into cache for faster access.