ARM7

Advanced RISC Machines are a set of CPUs that are based on the RISC architecture.

Architecture

Address bus

The address bus has 32b. Therefore, it can access 4GB of memory. The same memory is used for code and data as it follows Von Neumann architecture.

Program counter

The PC also has 32b. It contains the address of the next instruction. However since, each instruction is 32b = 4B long, the PC increments by 4 each time. So the two lower bits of the PC are insignificant.

Data bus

Is also 32b. Is used for reading/writing data and fetching instruction opcode. The instruction opcode will be given to the Instruction decoder to identify the operation. Data that is read from the data bus can be 8b, 16b or 32b. It will be given to Sign extender before being stored in a 32b register.

ALU

The ALU is also 32b long. It performs arithmetic on registers and then stores the result in registers as well, while updating the flag register.

Barrel shifter

It is a logic shifter. It can shift multiple times in one cycle. It is used to prescale an operand before giving it to the ALU. It can also act on a singler register, and can also rotate the data in a register.

Register file

ARM has a total of 37 registers, each 32b (4B) long. Among them, R0 - R15 are general purpose registers (GPRs). And among these GPRs, some are special registers like -

  • R15 - PC
  • R14 - LR
  • R13 - SP

Multiply accumulate (MAC)

It is used to perform multiply operation with accumulation.

MAC instruction

MAC R0, R1, R2, R3 is equivalent to R0 = R1 * R2 + R3

Address register

It holds the address of operands during LOAD and STORE instruction. It has its own incrementor that is independent of the ALU. The incrementor is significant in base index addressing mode.
attachments/arm7_dataflow.png

Features

ARM7 has 7 operating modes, 7 interrupts and 7 addressing modes.
ARM7TDMI -

  • Thumb instructions
  • Hardware debugging
  • Enhanced multiplications
  • ICE microcells for debugging

CPSR

CPSR stands for current status program register. It is a status register.

Bit Name Description
31 N Negative flag
30 Z Zero flag
29 C Carry flag
28 V Overflow flag
24 J Jazelle
7 I Interrupt mask
6 F Fast interrupt mask
5 T Thumb state
43210 Mode Operating modes select

The bits for selecting various operating modes are -

  • 1 0000 - User
  • 1 0001 - FIQ
  • 1 0010 - IRQ
  • 1 0011 - Supervisor
  • 1 0111 - Abort
  • 1 1011 - Undefined
  • 1 1111 - System

Operating modes

User mode

It is the normal mode in which all user programs are executed. It has limited access to memory and I/O flags. All other modes are entered through interrupts.

Fast interrupt mode

It is enabled when high priority interrupt is recevied from nFIQ pin. Nested interrupts are enabled in this mode. These interrupts are should be served with minimum delay.

Interrupt mode

It is enabled when interrupt is received from nIRQ pin. Nested interrupts are allowed. They are served with some delay.

Supervisor mode

It is enabled when RESET is triggered, to execute the BIOS program. It can be invoked via a software interrupts.

Abort mode

Abort mode is entered when an unsuccessful attempt is made to access memory. In this mode, some memory locations are not available.

Undefined mode

We enter undefined mode when a coprocessor instruction is encountered and not found.

Registers

There are a total of 16 (R0 - R15) + 1 (CPSR) registers in each mode. But some of these are banked (unique to each mode).

  • User/System have all registers common. So, a total of 17 so far.
  • FIQ mode has R8 - R12 unique for itself. So, a total of 22 so far.
  • Every other mode has its own uniqe SP, LR, SPSR (Saved program status register that is used to store the CPSR from the user/system mode when another mode is activated). That is 15 more, so we now have 37 registers in total.

Instruction sets

ARM

  • The default instruction set with CPSR.T = 0.
  • Has a total of 58 32b instructions with 15 GPRs and PC.
  • Can R/W in privileged mode.

Thumb

  • CPSR.T has to be set to 1 to activate.
  • Only has 30 16b instructions with 8 GPRs + 7 high registers and PC (So, I guess 15 GPRs?)
  • Cannot R/W.

Jazelle

  • A closed instruction set that requires licensing from ARM Limited and Sun Microsystems.
  • CPSR.T has to be 0 and J has to be 1.
  • Each instruction is 8b.

Conditional execution

Each instruction can be suffixed with EQ, GE, GT and so on to check with the status register and conditionally execute. This reduces branching.