8051 microcontroller
The Intel MCS-51 is commonly called the 8051. The 8051 is a Harvard architecture, CISC architecture single chip microcontroller. It initially used NMOS technology but later switched to CMOS, indicated by a C in their name, use less power.
Overview
| Feature | Description |
|---|---|
| RAM | 4 KB |
| ROM | 128 B |
| Timers | 2 |
| I/O pins | 32 |
| Serial port | 1 |
| Interrupt sources | 6 |
It has a 16 bit address bus and an 8 bit data bus.
Ports can be configured as input but setting them high and as output by setting them low.
The serial port is fully duplex, it can receive and transmit directly.
There were lots of versions of the 8051 manufactured by various companies like Atmel, Zilog among others. There were variants with different sizes of RAMs, fewer ports, ROM-less variants and many others.
Pin description
| Pin number | Pin name | Description |
|---|---|---|
| 40 | Main power source, is usually 5V. | |
| 32 - 39 | P0(.0 to .7) | Only bi-directional I/O port. Requires external pull up resistors. Used to multiplex lower order address bits when used to interface with external memory. |
| 31 | ALE (Address Latch Enable) |
When ALE = 0, P0 works as data bus. When ALE = 1, P0 works as address bus. |
| 30 | EA (External Access) |
When EA = 0, external memory interfacing is enabled. Only the program stored in external ROM is run. When EA = 1, external memory interfacing is disabled. The program in internal ROM is run then the program in external ROM is run. |
| 29 | PSEN (Program Store ENable) |
It is used with the EA pin in ROM-less systems to allow for storing program code in external ROM. Active low output pin, activates after a low pulse. |
| 21 - 28 | P2(.0 to .7) | I/O port that is used to multiplex higher order memory bits when interfacing with external memory. It is quasi bi-directional. |
| 20 | Ground. 0V. | |
| 18, 19 | XTAL1, XTAL2 | Used for interfacing an external crystal as system clock. |
| 10 - 17 | P3(.0 to .7) | 0 is RxD 1 is TxD Both of these are used for serial communication. 2 and 3 are used for external interrupts. 4 and 5 are used for T0 and T1 respectively. 6 and 7 are write and read pins |
| 9 | RESET | Set high for 2 machine cycle to reset all values. |
| 1 - 8 | P1(.0 to .7) | I/O port. Has internal pull up resistors. Quasi bi-directional. |
Memory organization
The 8051 usually has 128B of RAM and 4KB of ROM. The ROM can be expanded upto 64KB using external memory.
The RAM has 3 major divisions -
Register banks
The lowest 32B of RAM are used as register banks. There are a total of 4 register banks having 8B each. The registers R0 - R7 are stored in the selected bank.
When register bank 1 is selected, R0 to R7 are mapped to address 0x08 to 0x0F in that order.
A register bank can be selected using the RS1, RS0 bits in the PSW register.
Bit addressable memory
The next 16 bytes after the register banks are bit addressable memory.
16 B = 128 b.
So, the numbers 0x00 to 0x7F, when used with bitwise instructions, refer to these 128 b.
SETB and CLR are two such examples that can operate on individudal bits.
SETB 0x09 would set the bit at 0x09 in bit addressable memory, which is equivalent to the 2nd bit in the 2nd byte, or (0x21).1
Scratch pad area
The next 80B, 0x30 to 0x7F of internal RAM is called the scratch pad area. It is general purpose and is byte addressable. It can be accessed using both direct and indirect addressing modes.
Special Function Registers
SFRs are located after the scratch pad area from 0x80 to 0xFF. Although this space is 128B only 21 registers are defined. Some of these registers are byte addressable. The reason for this is to leave other locations empty for other manufacturers to fill while keeping it backwards compatible.
| Address | SFR |
|---|---|
| 0x80 0x90 0xA0 0xB0 |
P0 P1 P2 P3 |
| 0x81 | SP |
| 0x82 0x83 |
DPL DPH |
| 0x87 | PCON |
| 0x88 0x89 0x8A 0x8B 0x8C 0x8D |
TCON TMOD TL0 TL1 TH0 TH1 |
| 0x98 0x99 |
SCON SBUF |
| 0xA8 0xB8 |
IE IP |
| 0xD0 0xE0 0xF0 |
PSW A B |
PSW
Stands for Program Status Word. Contains several status flags and control flags.
| Bit | Purpose |
|---|---|
| 7 | Carry |
| 6 | Auxillary carry |
| 5 | F0 General purpose |
| 4 3 |
RS1 RS0 |
| 2 | Overflow |
| 1 | User defined |
| 0 | Parity |
DPTR
The data pointer register is a 16 bit register that is used to hold addresses. It acts as a base register in base relative addressing mode. (@DPTR + offset to find data)
SP
The stack pointer defaults to location 0x07 when reset which is R7 of register bank 1. On pushing, it increments and stores data at the new address.
PC
The program counter is a 16 bit register that also holds addresses. It holds the address of the next instruction. It defaults at 0x0000 when reset and increments after each instruction.
Machine cycle
Usually, an instruction on the 8051 takes 12 clock cycles to execute. 12 clock cycles are termed as one machine cycle.
There might be variants of the 8051 that take lesser or greater than 12 cycles as a machine cycle.
Some notable instructions like DJNZ, RET take 2 machine cycles to execute.
Instruction set
There are a total of 255 instructions. But only 111 of them are unique. Commands like ADD A, R0 and ADD A, R1 are counted as different to make up the 255 total. Of a total 256 possible opcodes, only 255 are implemented and 0xA5 is left empty. Of these 255 -
- 139 are 1B instructions
- 92 are 2B instructions
- 24 are 3B instructions